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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Power-Up
Power-Up
The following sequence must be used to power up the device. Unless specified other-
wise, this procedure is mandatory (see Figure 26 (page 42)). Power-up and initializa-
tion by means other than those specified will result in undefined operation.
1. Voltage Ramp
While applying power (after Ta), CKE must be held LOW ( ≤ 0.2 × V DDCA ), and all other
inputs must be between V ILmin and V IHmax . The device outputs remain at High-Z while
CKE is held LOW.
On or before the completion of the voltage ramp (Tb), CKE must be held LOW. DQ, DM,
DQS, and DQS# voltage levels must be between V SSQ and V DDQ during voltage ramp to
avoid latchup. CK, CK#, CS#, and CA input levels must be between V SSCA and V DDCA dur-
ing voltage ramp to avoid latchup.
The following conditions apply for voltage ramp:
? Ta is the point when any power supply first reaches 300mV.
? Noted conditions apply between Ta and power-down (controlled or uncontrolled).
? Tb is the point at which all supply and reference voltages are within their defined op-
erating ranges.
? Power ramp duration t INIT0 (Tb - Ta) must not exceed 20ms.
? For supply and reference voltage operating conditions, see the Recommended DC
Operating Conditions table.
? The voltage difference between any of V SS , V SSQ , and V SSCA pins must not exceed
100mV.
Voltage Ramp Completion
After Ta is reached:
?
?
?
?
V DD1 must be greater than V DD2 - 200mV
V DD1 and V DD2 must be greater than V DDCA - 200mV
V DD1 and V DD2 must be greater than V DDQ - 200mV
V REF must always be less than all other supply voltages
Beginning at Tb, CKE must remain LOW for at least t INIT1 = 100ns, after which CKE can
be asserted HIGH. The clock must be stable at least t INIT2 = 5 × t CK prior to the first
CKE LOW-to-HIGH transition (Tc). CKE, CS#, and CA inputs must observe setup and
hold requirements ( t IS, t IH) with respect to the first rising clock edge (and to subse-
quent falling and rising edges).
If any MRRs are issued, the clock period must be within the range defined for t CKb
(18ns to 100ns). MRWs can be issued at normal clock frequencies as long as all AC tim-
ings are met. Some AC parameters (for example, t DQSCK) could have relaxed timings
(such as t DQSCKb) before the system is appropriately configured. While keeping CKE
HIGH, NOP commands must be issued for at least t INIT3 = 200μs (Td).
2. RESET Command
After t INIT3 is satisfied, the MRW RESET command must be issued (Td). An optional
PRECHARGE ALL command can be issued prior to the MRW RESET command.
Wait at least t INIT4 while keeping CKE asserted and issuing NOP commands.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
40
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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相关代理商/技术参数
MT42L256M32D4KP-MS
制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk